Photolithographic patterns on an integrated circuit (IC) are often positioned with respect to existing structures in the IC using topographical alignment marks formed in existing patterned layers in the IC having surface height differences typically more than 10 nanometers with respect to adjacent regions of the IC or within the alignment marks. Light is reflected from the topographical alignment marks to measure the position of the IC. In some instances, a layer of material over the topographical alignment marks has low reflectivity, making measurement of the IC position problematic.